Custom IO and ESD Library Development

We offer IO and ESD solutions with extended voltage ranges up to 100 V, covering a wide range of foundry processes including TSMC, UMC, and Silterra, in 40nm, 65mn, 90mn, 0.13um, 0.18um, and 0.25um nodes.

We develop ESD IP on a regular basis, and our experience and portfolio allow us to quickly compile a semi- or fully-custom library based on your specifications. We develop custom libraries on an aggressive schedule, achieving best-in-class ESD clamp characteristics under latch-up, current balance optimization, and tight integration with your proprietary IP, and offer advantages over the standard libraries provided by foundries because we take into account your specific needs regarding form factor, system level capabilities, and test requirements.

Experimental Evaluation and Debugging Support

We also offer help in evaluating ESD/IO cells developed by us or by you, and can coordinate testing and qualification per common standards and models such as

• Human Body Model (HBM)
• Machine Model (MM)
• Charged-Device Model (CDM)
• TLP and vfTLP I-V characteristics
• Pulsed SOA
• IEC ESD and surge tests
• JEDEC latch-up testing

and failure analyses involving various techniques, including

• Liquid crystal
• PHEMOS
• Back-side emission
• OBIRCH
• TEM
• De-processing

Device Design and TCAD Validation Services for Custom IO and ESD Libraries

Our ESD device designs are based on EDA/TCAD validation using Symica Spice (http://www.symica.com) and Angstrom Design Automation DECIMM (http://www.angstromda.com), including

• Analog ESD circuit modeling and simulation in Spice
• Mixed-mode simulation for ESD
• Circuit simulation for entire ESD/IO pad ring emulating the full chip
• Latch-up analysis with DECIMM